/*--------- Registers for M1 ----------*/
register M1_srcip
{
    width: 32;
    instance_count: M1_SIZE;
}
register M1_dstip
{
    width: 32;
    instance_count: M1_SIZE;
}
register M1_proto
{
    width: 8;
    instance_count: M1_SIZE;
}
register M1_cnt
{
    width: 32;
    instance_count: M1_SIZE;
}

/*--------- Registers for M2 ----------*/
register M2_srcip
{
    width: 32;
    instance_count: M2_SIZE;
}
register M2_dstip
{
    width: 32;
    instance_count: M2_SIZE;
}
register M2_proto
{
    width: 8;
    instance_count: M2_SIZE;
}
register M2_cnt
{
    width: 32;
    instance_count: M2_SIZE;
}

/*--------- Registers for M3 ----------*/
register M3_srcip
{
    width: 32;
    instance_count: M3_SIZE;
}
register M3_dstip
{
    width: 32;
    instance_count: M3_SIZE;
}
register M3_proto
{
    width: 8;
    instance_count: M3_SIZE;
}
register M3_cnt
{
    width: 32;
    instance_count: M3_SIZE;
}

/*--------- Registers for M4 ----------*/
register M4_srcip
{
    width: 32;
    instance_count: M4_SIZE;
}
register M4_dstip
{
    width: 32;
    instance_count: M4_SIZE;
}
register M4_proto
{
    width: 8;
    instance_count: M4_SIZE;
}
register M4_cnt
{
    width: 32;
    instance_count: M4_SIZE;
}

/*---------- Register for Resubmission ----------*/
register resubmission_counter {
 width: 64;
 instance_count: 1;
}
/*----------*/

/*++++++++++ Register for Packet Count ++++++++++*/
register packet_counter {
 width: 64;
 instance_count: 1;
}

register ip_packet_counter {
 width: 64;
 instance_count: 1;
}

register prom_num_reg {
 width: 32;
 instance_count: 1;
}

register min_reg {
 width: 32;
 instance_count: 1;
}

register rand_reg {
 width: 32;
 instance_count: 1;
}
/*----------*/

